| 摘要 |
PURPOSE:To lessen the lowering of an output level by clamping the gate voltage of the 1st load transistor (TR) to a power voltage by the output of the 2nd boostihg circuit. CONSTITUTION:A level at a terminal 2 is determined by the ratio of the ON resistance of the 1st load TR3 which is connected to an output terminal 2 at the source, to a power source 29 at the drain and to the output point 11 of the 1st boosting circuit at the gate and that of the 1st driver TR4 which is connected to the terminal 2 at the drain, grounded at the source and to a control input terminal 1 at the gate. The TR33 is connected to the power source 29 at the drain, to the gate of the TR3 at the source, and to the output point 18 of the 2nd boosting circuit at the gate through a boosting capacitor (C) 34 to clamp a voltage at the output point 11 to a power voltage V. To the terminal 2, a boosting C27 whose one terminal is connected to the output point 26 of the 3rd boosting circuit is connected. When a level at the output point 18 rises, the gate voltage of the TR3 is clamped to the power voltage through the C34 and TR33, so the lowering of the voltage level at the terminal is reduced. |
