Folded bit line-shared sense amplifiers.

摘要

For sensing the logic state of an accessed memory cell in a dynamic MOS random access memory, a shared sense amplifier (14) is positioned between and coupled to first and second bit lines (A,B) via first and second isolation transistors (10,12) and is also positioned between and coupled to third and fourth bit lines (C,D) via third and fourth isolation transistors (16,18). In use, a memory cell capacitor (26) is coupled to a selected bit line (A) and a dummy cell capacitor (CD) is coupled to the adjacent bit line (B). A decoding circuit (64,76) selectively activates the shared sense amplifier (14) to sense a voltage difference between the bit lines and to latch into a corresponding logic state for reading by input/output buss lines (17,19). After the logic state is read, the circuit (64,76) enables the memory cell capacitor (26) to be refreshed for further sensing.