发明名称 REFERENCE AND UPDATE RECORDING CONTROL SYSTEM
摘要 PURPOSE:To protect information in a block by performing error detection by adding parity bits to reference bits and update bits, and considering reference and update to have be done when an error is detected. CONSTITUTION:A memory RCS is provided with reference bits R, update bits C and parity bits P corresponding to blocks of a main storage device; and a reference bit R corresponding when referred to is set to a 1, and an update bit C corresponding when updated is set to a 1 while the reference bit R and update bit C are cleared by a program. A parity bit P is set according to odd parity. Namely, when readout data from the memory RCS has an error, and when date set in a register RCB has an error, the reference bit R and update bit C are set to 1s and consequently, error detection is achieved even if the update bit C is not set to the 1, but to the 0 erroneously, so that information in blocks is retained.
申请公布号 JPS5786194(A) 申请公布日期 1982.05.29
申请号 JP19800159846 申请日期 1980.11.13
申请人 FUJITSU KK 发明人 NODA KATSUNOBU;FUJIMAKI HIDEAKI
分类号 G06F12/12;G06F11/10;G06F12/10;G06F12/16 主分类号 G06F12/12
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