| 摘要 |
PURPOSE:To prevent the occurrence of an undesired overrun for a high-speed input/output device, etc., by releasing once the occupation of a high-speed bus through a bus converter. CONSTITUTION:Both signals IOP and DTSD are received at a mode timing circuit 14, and the address information ADR is latched to an address latching circuit 10. An open signal OPEN is raised up, and at the same time the circuit 14 transmits a service-out signal SVOI to the side of a low-speed bus to carry out the control so as to transmit the contents of the circuit 10. When receiving a service in signal SVI of a low-speed input/output device, the circuit 14 lowers the signal OPEN to give an occupation request for the high-speed bus. Then the data is sent to the side of the high-speed bus via a data driver 13 when a bus occupation permission signal OPENAV is received. And a data confirmation signal DTAK is transmitted. |
