| 摘要 |
PURPOSE:To process data in a high speed by placing plural number of intermediate registers in the middle position between the first and the second instruction registers and holding different instructions in the plural number of intemediate registers at the same time to eliminate an idle time. CONSTITUTION:An instruction that controls read of data for processing is set to a read stage register 1, and No.1-No.3 start-up registers 3-5 that are to be the destination of transfer of the instruction that was set to this register are selected by No.1 counter 2. The configuration is so arranged that the instruction set to the register 1 can be held temporarily by these registers 3-5, and the instructions from these registers 3-5 are added to one side of AND circuits 7-9 respectively and the control signal from a counter 6 is added. And by the control signal of the counter 6, the output of the registers 3-5 is selected from the circuits 7-9, which is input to a write stage register 10 which controls writing. Thereby an idle time is eliminated and the data is processed in high speed. |
