| 摘要 |
PURPOSE:To reduce the number of timing circuits and external terminals by half by providing the titled circuit with a flip-flop (FF) circuit processing a composite synchronizing signal as a clock signal input and an output of a single stabilizing circuit which corresponds to a horizontal synchronizing signal as a data input. CONSTITUTION:A composite synchronizing signal applied to an input terminal 6 is supplied to a single multiplexer as a trigger input and also supplied to a D-FF circuit 4 as a clock signal. When the single multiplexer 2 is triggered, a capacitor 12 starts to be charged by the trailing edge of each signal pulse and is charged up to the leading edge of the succeeding signal and the discharging circuit of the capacitor is formed synchronously with the leading edge of a horizontal synchronizing signal. Since a pulse C corresponding to the horizontal synchronizing signal is fetched if the threshold level of the single multiplexer 2 is selected, the pulse C is applied to the data input of the D-FF 4. Consequently, an output signal discriminating the division of a vertical synchronizing signal is fetched from an output terminal 20 of the D-FF 4. |
