Method of generating techfile having reduced corner variation value

摘要

A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.

主权项

1. A method of generating a techfile corresponding to a predetermined fabrication process, the method comprising:
determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of the electrical characteristic from one or more sample integrated circuit chips fabricated by the predetermined fabrication process; calculating a reduced variation value by applying a scaling factor to the corner variation value; and generating, using a processor, the techfile based on the typical value and the reduced variation value, wherein the techfile is provided for generating a layout design for fabricating additional integrated circuit chips by the predetermined fabrication process.