| 摘要 |
PURPOSE:To perform high-performance, high-efficient processing with less communication overheads by allotting a part of the main storage of a prescribed processor for a common memory, and attaining access from its central processing unit and interface control part. CONSTITUTION:A CPU14 reads an instruction out of an MM11 to generate actual addresses of the MM11 and a common memory 26, and sends them to an interface control part (ICL) 13 through a memory controller (MCU)12, thus requesting data transfer. For transfer from the MM11 to the common memroy 26, an address of the common memory 26 is sent from the ICL13 through a path 150 to make a write indication to the common memory 26, and data are read out of the MM11 and transferred successively to the ICL23. A processor 10 executes an instruction for data transfer between the main memory (MM)11 and the common memory 26 in the MM21 of a processor 20. |
