| 摘要 |
PURPOSE:To obtain a semiconductor integrated circuit which has a reduced level of power consumption and an decreased time of delay, by supplying different levels of voltage to the base of the constant current source transistor of a current switching logical circuit (CML). CONSTITUTION:The different levels are set for constant current voltages VCS3 and VCS4 of constant current source transistors QS2 and QS1 of current switching logical circuit (CML) of a double input AND circuit. The amplitude is controlled by the different levels of voltages VCS3 and VCS4 in consideration of the margin that is required for the output voltage G02. The amplitude is decreased by making use of an amplitude Vl which is required for the CML. Thus the delay of time is decreased greatly, and the reduction of electric power is made possible with a reduction of current. This device is effective to such a circuit in which the resistance is fixed with a large-scale integrated circuit, a gate array, etc. |
