| 摘要 |
PURPOSE:To solve jitters without increasing the number of bits while maintaining high transfer efficiency, by setting the center frequency of a transfer clock in a jitter correcting circuit which uses a variable delay element according to the amount of generated jitters. CONSTITUTION:A horizontal synchronizing signal and a burst signal are separated from a jitter-corrected output obtained by controlling a variable delay element by a transfer clock, and then compared with reference signals to obtain a jitter detection output, which is supplied as a control input to a variable oscillating circuit. In this jitter correcting circuit, a jitter detection output outputted from an adding circuit 11 is detected by a detecting circuit 12. The obtained detected level is applied to a variable oscillating circuit 3 as a DC bias for prescribing the center frequency of the transfer clock, so the best jitter correction of any reproduced video signal is performed regardless of the level of the jitters without increasing the number of bits of a variable delay line. |
