发明名称 Methods of fabricating embedded electronic devices including charge trap memory cells
摘要 A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer and a sacrificial insulation layer on a substrate having a first region and a second region. The tunnel insulation layer, the charge trap layer and the sacrificial insulation layer which are stacked on the second region of the substrate are selectively removed. A well region is formed in an upper region of the second region of the substrate. The sacrificial insulation layer remaining over the first region is removed to expose the charge trap layer remaining over the first region. A blocking insulation layer and a gate insulation layer are formed on the exposed charge trap layer over the first region and on the second region of the substrate, respectively.
申请公布号 US9508733(B1) 申请公布日期 2016.11.29
申请号 US201514885371 申请日期 2015.10.16
申请人 SK Hynix Inc. 发明人 Lee Tae Ho;Kwon Young Joon;Park Sung Kun
分类号 H01L27/115;H01L21/28;H01L21/02;H01L21/311;H01L21/265;H01L21/266;H01L29/51 主分类号 H01L27/115
代理机构 IP & T GROUP LLP 代理人 IP & T GROUP LLP
主权项 1. A method of fabricating an embedded electronic device including charge trap memory cells, the method comprising: forming a tunnel insulation layer, a charge trap layer and a sacrificial Insulation layer on a substrate having a first region and a second region; selectively removing the tunnel insulation layer, the charge trap layer and the sacrificial Insulation layer which are stacked on the second region of the substrate; forming a well region in an upper region of the second region of the substrate; removing the sacrificial insulation layer remaining over the first region to expose the charge trap layer remaining over the first region; and forming a blocking insulation layer and a gate insulation layer on the exposed charge trap layer over the first region and on the second region of the substrate, respectively.
地址 Gyeonggi-do KR