| 摘要 |
PURPOSE:To obtain a highly integrated circuit, by providing a multiple layer structure for an input output aligning circuits and other parts, thereby reducing the chip area as small as possible. CONSTITUTION:The input output aligning circuit parts 6 and 7 are located on a dielectric layer 10. On the layer 10, one layer of the dielectric layer 11 is formed, and a resistor 12 and RC feedback circuits comprising capacities fromed by 13- 11-41 and 13'-11-51 are formed on the layer 11. Therefore, the integration degree of the circuit is increased by the cubic expansion instead of the planar expansion. This is effective in the viewpoint of the efficiency of the chip area. When the dielectric constant epsilon of the dielectric layer 10 is selected so that it is larger than the dielectric constant of the GaAs substrate, the size of the aligning circuit pattern can be reduced in inversely proportional to epsilon1/2. |
