Optimal stacked transistor placement to increase single event transient robustness

摘要

Circuitry may include a substrate with an input and an output circuit coupled in series at an intermediate node. The output circuit may have an output transistor and a stack transistor coupled in series between an output node and a voltage supply terminal. The two circuits may be placed on the substrate such that a single event transient charge injected into a sensitive diffusion of the intermediate node is shared through the substrate with the sensitive diffusion of the stack transistor of the output circuit. The charge sharing may reduce the recovery time at the output node and help to reduce the recovery time at the intermediate node, thereby providing increased single event transient robustness and reducing the probability of a permanent flip of the intermediate node and the output node of the circuitry.

主权项

1. Circuitry, comprising:
a substrate; a first circuit with an input node, an output node, and first and second stacked transistors, wherein the first stacked transistor is coupled between the output node and the second stacked transistor, and wherein the first circuit is formed in the substrate; a second circuit with an output node, wherein the output node of the second circuit is coupled to the input node of the first circuit, and wherein the second circuit is formed in the substrate; and a transistor in the second circuit having a pair of source-drain diffusions, wherein one of the source-drain diffusions of the transistor is coupled to the input node of the first circuit, wherein the transistor is placed at a first distance in the substrate from the second stacked transistor and at a second distance in the substrate from the output node of the first circuit, wherein the second distance is longer than the first distance, and wherein the first stacked transistor, the second stacked transistor, and the transistor of the second circuit are of a predetermined channel type.