发明名称 |
Optimized fused-multiply-add method and system |
摘要 |
A fused-multiply-add system is disclosed. The fused-multiply-add system includes a multiplier to multiply first and second operands and to provide at least one product. The fused-multiply-add system also includes an alignment shifter for aligning a third operand with the at least one product to provide an aligned third operand. The fused-multiply-add system also includes an adder and a subtractor coupled to the multiplier and the alignment shifter for performing two asymmetrical additions in parallel paths. The fused-multiply-add system also includes at least one leading zero counter for counting a number of leading zero bits provided by at least one of the adder and the subtractor to provide at least one normalization shift amount. Finally, the fused-multiply-add system includes a multiplexer coupled to the adder and the subtractor for providing an appropriate output based upon a sign bit. |
申请公布号 |
US9519458(B1) |
申请公布日期 |
2016.12.13 |
申请号 |
US201414248130 |
申请日期 |
2014.04.08 |
申请人 |
Cadence Design Systems, Inc. |
发明人 |
Chen David H. C.;Huffman William A. |
分类号 |
G06F7/57;G06F7/483 |
主分类号 |
G06F7/57 |
代理机构 |
Schwegman Lundberg & Woessner, P.A. |
代理人 |
Schwegman Lundberg & Woessner, P.A. |
主权项 |
1. A fused-multiply-add (FMA) system comprising:
a multiplier multiplying a first operand and a second operand and providing at least one product of the first and second operands; an alignment shifter aligning a third operand with the at least one product and providing an aligned third operand; an adder and a subtractor coupled to the multiplier and the alignment shifter, the adder and the subtractor in parallel paths; at least one leading zero counter providing at least one normalization shift amount by counting a number of leading zero bits provided by at least one of the adder and the subtractor; and a multiplexer having a first multiplexer input coupled to an adder output of the adder and a second multiplexer input coupled to a subtractor output of the subtractor and, based upon a control signal input of the multiplexer, providing the first multiplexer input or the second multiplexer input as an output of the multiplexer. |
地址 |
San Jose CA US |