METHODS OF FORMING STAIRCASE-SHAPED CONNECTION STRUCTURES OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

摘要

Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

主权项

1. A method of fabricating a three-dimensional semiconductor device, comprising:
sequentially stacking a plurality of horizontal layers on a substrate to form a stack; patterning some of the horizontal layers to form a first staircase region with at least one first multi-level stair; patterning others of the horizontal layers to form a second staircase region with at least one second multi-level stair; and patterning both of the first and second staircase regions at once to form single-level stairs in each of the first and second multi-level stairs, wherein the first and second staircase regions are formed in such a way that a distance therebetween is larger than a width of each of the single-level stairs therein.