发明名称 MEMORY READING CIRCUIT
摘要 PURPOSE:To obtain a large amplitude for a reading signal of a memory, by boosting selectively the voltage of a data line in response to the reading voltage. CONSTITUTION:An input pulse BT is applied to bootstrap circuits (Q1, Q2) after detecting the set signal of a sense amplifier SA is turned off. In this case, the voltage of the digit sense line that has a level higher than the voltage Vth exceeds quickly the voltage VDD owing to the effect of capacity Cb. Then a high level of voltage is generated at a high speed to an output V0(-V0). The voltage of the other digit sense line having the voltage of level 0 is kept at level 0 regardless of application of pulse BT. Therefore the working of a peripheral circuit can be accelerated.
申请公布号 JPS58179991(A) 申请公布日期 1983.10.21
申请号 JP19830030715 申请日期 1983.02.28
申请人 HITACHI SEISAKUSHO KK 发明人 ITOU KIYOO;CHIBA YUKINOBU;SHIMOHIGASHI KATSUHIRO
分类号 G11C11/41;G11C7/12;G11C11/409;G11C11/419 主分类号 G11C11/41
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