FinFET for device characterization

摘要

A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

主权项

1. A FinFET device for characterization, comprising:
a dielectric material layer; a plurality of vertical active fins disposed directly over the dielectric material layer, each vertical active fin including a P+ contact area, a vertical P-type LDD fin, a vertical P-type body fin, a vertical N-type LDD fin, and an N+ contact area, wherein the vertical P-type LDD fin is formed between the P+ contact area and the vertical P-type body fin, and the vertical N-type LDD fin is formed between the vertical P-type body fin and the N+ contact area to provide a PN junction, wherein the vertical P-type LDD fin includes a p-type LDD doped feature and wherein the vertical N-type LDD fin includes an n-type LDD doped feature; a gate electrode formed over the plurality of vertical active fins and separated therefrom by a gate dielectric layer,
wherein the gate electrode has a first portion disposed over the plurality of vertical active fins and having a first width in a first direction and a second portion having a second width in the first direction that is greater than the first width,wherein the second portion of the gate electrode includes a first vertical sidewall opposite the plurality of vertical active fins and extending from the dielectric material layer to a first height, and the second portion includes a second vertical sidewall opposite the plurality of vertical active fins and extending from the first height to a topmost surface of the gate electrode,wherein the first vertical sidewall and the second vertical sidewall are offset such that a surface extends between the first vertical sidewall and the second vertical sidewall, andwherein at least one of the p-type LDD doped feature and the n-type LDD doped feature extends from the gate dielectric layer to the dielectric material layer; and a spacer layer including a first portion disposed directly over the vertical P-type LDD fin and a second portion disposed directly over the vertical N-type LDD fin, wherein the first and the second portions are formed on sidewalls of the gate electrode.