| 主权项 |
1. A method for fabrication of a semiconductor device, the method comprising:
forming a first gate in a first region of a substrate structure, a second gate in a second region of the substrate structure, a third gate in a third region of the substrate structure, and a fourth gate in a fourth region of the substrate structure so that there is defined on the substrate structure a first field effect transistor having the first gate, a second field effect transistor having the second gate, a third field effect transistor having the third gate, and a fourth field effect transistor having the fourth gate, wherein the first, second, third, and fourth gates have different gate configurations; and, doping the substrate structure in the regions of the first, second, third, and fourth field effect transistors so that the first and second field effect transistors have a common substrate structure doping configuration and the third and fourth field effect transistors have a common substrate doping; wherein: the fabrication is performed so that the first field effect transistor and the second field effect transistor have a common first channel polarity, and the third field effect transistor and the fourth field effect transistor have a common second channel polarity opposite the first channel polarity; and, the fabrication is performed so that the first field effect transistor includes a first threshold voltage, the second field effect transistor includes a second threshold voltage, the third field effect transistor includes a third threshold voltage, and the fourth field effect transistor includes a fourth threshold voltage, and, the first, second, third, and fourth threshold voltages are different threshold voltages; and, the fabrication is performed so that a first gate stack of the first gate, a second gate stack of the second gate, a third gate stack of the third gate, and a fourth gate stack of the fourth gate have a common gate dielectric layer and further so that a material configuration of the gate dielectric layer is common between the first region having the first gate, the second region having the second gate, the third region having the third gate, and the fourth region having the fourth gate; and, the fabrication is performed so that the first and second gate stacks have a common gate material sequence of the gate dielectric layer, a first conductive capping layer, a second conductive capping layer, a first work function layer, a second work function layer, an encapsulation layer, and a metal fill layer, wherein a thickness of the first work function layer in the first gate stack is different from a thickness of the first work function layer in the second gate stack; and the fabrication is performed so that the third and fourth gate stacks have a common gate material sequence of the gate dielectric layer, the first conductive capping layer, the second conductive capping layer, the second work function layer, the encapsulation layer, and the metal fill layer, wherein a thickness of the second work function layer in the third gate stack is different from a thickness of the second work function layer in the fourth gate stack. |
