发明名称 INPUT DATA PROCESSING SYSTEM OF SUPERVISION AND CONTROL SYSTEM
摘要 PURPOSE:To attain high speed processing, by providing a microprocessor exclusive use for bit slicing for the input data processing from a terminal controller side. CONSTITUTION:An LU controller 19 as the microprocessor exclusive use for the bit slicing, an LU operating section 20 and an LU memory 21 are connected to a local bus 14. A data via a network 2 or directly from the terminal controller side is stored to a memory 1B via an interface 1A of a CPU1. A CPU1C transfers a data for one block's share to the LU memory 21 so that the data stored in the memory 1B is processed by the LU controller 19, and gives an execution start command for bit converting processing to the LU controller 19. The LU controller 19 performs the bit converting processing sequentially as to the data for one block's share of the said LU memory 21 in high speed by using the LU operating section 20 according to the bit conversion program stored in the LU memory 21 in advance.
申请公布号 JPS58212296(A) 申请公布日期 1983.12.09
申请号 JP19820095711 申请日期 1982.06.04
申请人 MEIDENSHA KK 发明人 HATANO TOMOTOSHI
分类号 H04Q9/00;G06F13/12 主分类号 H04Q9/00
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