| 摘要 |
PURPOSE:To realize simple circuit construction to test quality of respective logic elements in the logic circuit by every element unit by a method wherein the whole input-output terminals of the logic element to be made as the subject of the quality test are made to be in the enabled condition independently of the other logic elements by one probe in the logic circuit to be tested. CONSTITUTION:When quality of the logic circuit 1 to be tested is to be tested as the whole, the enabling terminals E of the whole logic elements 3-5 are made to a high level by applying the high level to an outside terminal 2, and the whole input-output terminals are held in the enabled condition. Moreover, when quantities of the logic elements 3-5 are to be tested by every element unit, the enabling terminals E of the whole logic elements 3-5 are made to a low level by applying the low level to the outside terminal 2 at first, and accordingly the whole input-output terminals are made to the disenabled condition. Then the probe 15 is made to come in contact with a probing point 6 connected to the enabling terminal E of the logic element (the logic element 3, for example) to be made as the subject of the quality test, the high level is applied thereto, and the whole input-output terminals of the logic element 3 thereof are made to be in the enabled condition. |
