发明名称 COMPLEMENTARY MOS LOGICAL CIRCUIT
摘要 PURPOSE:To attain multi-stage cascade connection, by taking a logical section with series connection of plural N-channel depletion MOSFETs and inserting a P-channel MOSFET between one end of the logical section and an output terminal for decreasing number of elements. CONSTITUTION:The MOSFETs 51, 52, 53 connected in series in the logical section 50 are all turned on when three logical signals A, B, C are at a high level. A connecting point 57 is set to a level higher than the potential of a power supply. Since the MOSFET55 turns on, an output terminal 54 is set to a high level. When at least one of the logical input signals A, B, C is at a low level, the FET is turned off. The potential at the connecting point 57 is fixed to an absolute value of the threshold voltage of the N-channel depletion MOSFET in this case. The FET55 is turned off. The output terminal 54 is kept to a low level with the presence of a resistor 56. The logical signal of the logical input signals A, B, C is obtained at the output terminal 54.
申请公布号 JPS5916425(A) 申请公布日期 1984.01.27
申请号 JP19820126105 申请日期 1982.07.20
申请人 TOKYO SHIBAURA DENKI KK 发明人 KOIKE HIDEJI
分类号 H03K19/0948 主分类号 H03K19/0948
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