| 摘要 |
PURPOSE:To reduce number of times of interrupt to a CPU in the case of data transfer by providing a CPU, a memory section and a transfer control section in a processing element and providing an arrangement data section and a header section on the memory section. CONSTITUTION:A processing element (PE) 1 having a CPU 10 and a memory section 11 is provided with a transfer control section 12. The control section 12 is provided with an address latch means 12-4, a data number latch means 12-5 and a count means 12-6 counting a data number. Moreover, the control section 12 is provided with a comparator means 12-0 comparing values of the latch means 12-5 and the count means 12-6 and with an interrupt control information latch means 12-l, in which an interrupt signal 1 or a noninterrupt signal 0 is described as interrupt control information. Based on the output of the comparator means 12-0, either the interrupt control information 1 or 0 is sent to the CPU 10. Thus, number of times of interrupt of the PE to the CPU is considerably decreased. |
