| 摘要 |
PURPOSE:To obtain a gate array LSI master system in which large blocks such as RAMs, registers, counters can be readily designed in wirings in size by providing a plurality of basic cell rows in parallel in a direction perpendicular to the basic cell row by providing wiring regions of the prescribed interval between the rows. CONSTITUTION:The unit cells 52 are aligned adjacent to one another to form a basic cell row 3. For example, a logic block 51-1 is composed of a basic cell 2, and a logic block 51-2 is composed of two basic cells 2. The block 51-2 is composed of 4 unit cells, but wirings between the unit cells are dispersed in four directions as shown by arrows, and the mixing degree of the wirings is alleviated. The area margin for extending the wirings to the block boundary upper terminal position can be reduced to 1/2 degree as compared with a drawing (a). This is beause the length of the same function logic block faced with the wiring region 4 is shorter in the drawing (b) by 50% than the case of the drawing (a). From the above point, large block such as RAMs, registers, counters can be composed in high area efficiency. |
