| 摘要 |
PURPOSE:To enable to stably drive an induction motor which suppresses the fluctuation of the output voltage and drives the motor by providing an FF circuit which receives as a clock the input pulse signal of a time integration counter between an address designating counter and a converter and synchronizing two pulse signals. CONSTITUTION:An FF circuit 36 which employs as clock the output pulse signal of an oscillator 11, i.e., the input pulse signals of time integration counters 9a, 9b and 10a, 10b between an address designating counter 4 and a voltage-to-frequency converter 3, thereby synchronizing two pulse signals. Thus, the input signal of the counter 4, i.e., the output signal of the FF circuit 36 always varies when the output pulse signal of the oscillator 11 falls. Accordingly, the pulse width of the output signal of the comparator 8a always becomes constant, and the inverter output voltage becomes constant. Consequently, the vibration of the induction motor can be reduced, and can be stably driven. |
