发明名称 DIGITAL PLL CIRCUIT
摘要 PURPOSE:To attain phase locking operation by detecting a frequency of frequency-dividing ratio charge evey time the result of phase comparison is obtained for a prescribed number and controlling the number of stages of a reversible counter means controlling the frequency of the frequency-dividing ratio charge so as to decrease the locking time. CONSTITUTION:Whether or not the frequency of frequency-dividing ratio change is larger in any direction is detected easily by monitoring an output of an up- down counter 13. Whether or not the result of phase comparison is obtained for a prescribed numbe is detected easily by counting the number by a counter 27. Every time the result of phase comparison of a prescribed number is counted by the counter 27, the output of the up-down counter 13 is monitored and when the number of stages of the counter 13 is controlled in response to the result of monitor, the locking time is decreased for attaining the phase locking.
申请公布号 JPS5995734(A) 申请公布日期 1984.06.01
申请号 JP19820205457 申请日期 1982.11.25
申请人 HITACHI SEISAKUSHO KK 发明人 KOSUGE SHIYOUJI;OGAWA MAKOTO;TOMOOKA KEIJI;SEKIHARA SHINJI
分类号 H03L7/06;H03L7/00 主分类号 H03L7/06
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