| 摘要 |
PURPOSE:To attain a two-phase colok pulse having less time delay, by making the input of the first row, where two stages of inverters are connected in series, and the input of the second row, where a gate and an inverter are connected in series, common and giving the output signal of the inverter of the first stage of the first row to both gate electrodes of the gate. CONSTITUTION:Two stages of inverters consisting of FETs 5-8 are connected in series to constitute the first row. An inverter consisting of FETs 9 and 10 and a transmission gate consisting of MOSFETs 15 and 16 are connected in series to constitute the second row. Both gates of FETs 15 and 16 are connected to the output of the inverter consisting of FETs 5 and 6. Gates of FETs 5 and 6 and sources of FETs 15 and 16 are connected to an input terminal 1. By this constitution, the two-phase clock pulse having less time delay is generated from the inverter of the rear stage in each row. |
