ECC bypass using low latency CE correction with retry select signal

摘要

A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

主权项

1. A controller for a memory device of a computer system comprising:
a read data line which receives uncorrected data with correction information for a memory address corresponding to requested data which is requested by a requesting unit of the computer system; a bypass path for transmitting the uncorrected data with the correction information to the requesting unit, said bypass path having a bypass latency; a plurality of error correction units which provide different complexity levels of error correction and have different correction circuit latencies, each of the correction circuit latencies being greater than the bypass latency, wherein there are at least three error correction units including a 2-bit correction unit, a 4-bit correction unit, and an 8-bit correction unit; and control logic which first transmits the uncorrected data with the correction information from said read data line to the requesting unit using said bypass path and, in response to a retry select signal from the requesting unit indicating an error in the uncorrected data having a specific complexity level, second transmits the requested data as corrected data from said read data line to the requesting unit using a selected one of said error correction units based on the retry select signal, wherein the correction circuit latency of the selected error correction unit adds a minimum latency necessary to provide complete correction of the uncorrected data; and a persistent error detection circuit which identifies the memory address of the requested data to be defective when an error is repeatedly indicated for the address by multiple retry select signals.