| 发明名称 |
Multilevel controller for a cache memory interface in a multiprocessing system. |
| 摘要 |
<p>A two level controller has been described for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. </p> |
| 申请公布号 |
EP0121373(A2) |
申请公布日期 |
1984.10.10 |
| 申请号 |
EP19840301838 |
申请日期 |
1984.03.19 |
| 申请人 |
BURROUGHS CORPORATION (A MICHIGAN CORPORATION) |
发明人 |
STECKLER, THOMAS MICHAEL |
| 分类号 |
G06F15/16;G06F9/28;G06F12/08;(IPC1-7):11C9/06 |
主分类号 |
G06F15/16 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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