| 摘要 |
PURPOSE:To compensate the drop of the boosting level of a word line and to ensure the full writing to a memory capactor by adding a level compensating circuit which detects the drop of the word line selecting level and recovers the dropped level up to the level of the power supply voltage. CONSTITUTION:The level differences VH and VL appear at complelementary data lines DL and DL by a word line selection timing singnal phix. A sense amplifier SA is activated by a timing signal phipa1, and an FETQ8 is turned on by a timing signal phipa2. Then the data line of low level VL is quickly changed to a low level, and this low level is transmitted to the work line by coupling. Thus the boosting voltage of the signal phix is dropped. An FETQ11 of a level compensating circuit LV is turned off, and the gate voltage of an FETQ 10 is set at a high level to recover the level of the signal phix up to the power supply voltage Vcc. Then an active restoring circuit AR is actuated to recover the high level up to the Vcc and written again to a memory capacitor Cs through an address selecting MOSFETQm. |
