发明名称 METHOD OF FIXING ELECTRIC TERMINAL
摘要 <p>A chip mounting device which is hereinafter also referred to as an "interconnection preform placement device", includes a retaining member having a predefined pattern of holes in which are positioned preforms of joint-forming material such as solder. Each preform is of a predefined configuration and has a height or length greater than is cross-sectional dimension. The preform retains its general configuration after the interconnection or soldering process to form a resilient joint which is more capable of withstanding stress, strain and fatigue. A method of forming resilient interconnections comprises placing the interconnection preform placement device between parallel patterns of electrically conductive elements, such as the conductive pads on an electronic component and a circuit board, and effecting the bonding of the conductive elements with the preforms.</p>
申请公布号 JPS6041779(A) 申请公布日期 1985.03.05
申请号 JP19830149830 申请日期 1983.08.17
申请人 FUJITSU KK 发明人 WATANABE AKIRA
分类号 H01R9/16;B23K3/06;B23K35/02;H05K3/32;H05K3/34;H05K3/40;H05K13/04 主分类号 H01R9/16
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