| 摘要 |
PURPOSE:To decrease both information transfer frequency and arithmetic frequency in order to attain a calculation at a high speed, by performing the arithmetic processing with an instruction to carry out a basic operation while giving a parallel array shift to the arithmetic result by an array cache memory. CONSTITUTION:When calculations SIGMAXi and SIGMAXi<2> are carried out among those basic arithmetics to obtain the correlation of the 2-dimensional information, data X1-X16 are loaded to the right (4X4) areas of a cache memory 3 from a main memory by an indication of a controller 1. Then a plane left shift 2 is given to the memory 3 four times to shift the data X1-X16 to the left (4X4) areas. Then S1=X and S2=X are set to an array processor PEi of an SIMD type computer 2, and the once plane shift 1 is executed to the memory 3. The processor PEi loads data from a memory element MEi-j of the lower memory 3 of its own to satisfy S1=S1+X and S2=S2+X<2>. Hereafter the prescribed steps are carried out. |
