发明名称 PSEUDO ERROR GENERATION SYSTEM
摘要 PURPOSE:To facilitate incorporation in a test diagnostic program for error occurrence and inspection results by generating various reproducible pseudo errors which may be repeated automatically and easily. CONSTITUTION:The pseudo error generation counter in a pseudo error generation counter circuit 12 is set to an optional value by an access circuit 9. The pseudo error generation counter is set initially to ''0'' and counts up with the rise of a stepping signal S500 outputted from a counter stepping circuit 10 to an output line 500, i.e. signal DMAACK. Respective bit outputs of the pseudo error generating register in a pseudo error generating register circuit 13 are inputted to AND gates 14, 15, 16, and 17 through error enable lines 301, 302, 303 and 304 respectively. Respective bits of the pseudo error generating register are set by an access circuit 11 to logic ''0'' or ''1''. Consequently, incorporation in a test diagnostic program the debugging and evaluation of a systematic error processing routine and error processing routine inspection is facilitated.
申请公布号 JPS60121853(A) 申请公布日期 1985.06.29
申请号 JP19830229522 申请日期 1983.12.05
申请人 NIPPON DENKI KK 发明人 KAMIYAMA TOSHIHIRO
分类号 H04L29/14;H04L13/00 主分类号 H04L29/14
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