| 摘要 |
The system comprises an address translation buffer (1) has entries each including a valid flag (V), a logical address field (LOG ADD), and a physical address field (PHY ADD), a memory array (10) having copies of the valid flag and the physical address field, and a purge register (7) for storing information showing a portion of the contents of the address translation buffer to partially purge the latter. In case of no coincidence between the physical address of the address translation buffer (1) and the contents of the purge register (7), the ordinary access processing can be carried out, and when the entry of the memory array (10) is accessed in turn and the coincidence between the physical address in the memory array and the contents of the purge register occurs, the partial purge is performed by clearing the valid flags of the corresponding entries of the address translation buffer (1) and the memory array. Thus, the partial purge processing can be carried out separately from the ordinary access processing, and the parformance efficiency, particularly for the application of this invention to a pipeline system or a virtual machine, can be increased. |
