发明名称 CONTROL SYSTEM OF TRI-STATE LOGICAL CIRCUIT
摘要 PURPOSE:To prevent a tri-state logical circuit from being damaged because of bus fight by providing a suppressing potential generating means transmitting and holding a suppressing potential to a state control input terminal of a tri- state logical circuit. CONSTITUTION:When a voltage VCC is increased from a zero potential attended with application of power and reaches a collector-emitter voltage of a transistor (TR) TR3, since a system set signal is a zero potential before application, the voltage is applied to a base of the TR3 via a resistor R3, the R3 is turned on and a collector potential of the TR3 is suppressed to zero potential. The TR1, TR2 are both turned off attended with the operation and this state is maintained.
申请公布号 JPS60130919(A) 申请公布日期 1985.07.12
申请号 JP19830240370 申请日期 1983.12.20
申请人 FUJITSU KK 发明人 NARITA YOSHIAKI
分类号 H03K19/0175;H03K19/003;H03K19/082 主分类号 H03K19/0175
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