| 摘要 |
PURPOSE:To allow bus release without fail by terminating read and write signals within a certain period in terms of the system where plural processors are connected by a bus and by releasing the bus temporarily so as to allow a retrial at the time of failure due to the response condition. CONSTITUTION:If a processor is of a bus master, a bus control part 100 transmits a bus requirement (BREQ) signal to an arbiter 13 when an action stop signal (BUSS) is not on, and waits a bus permission signal from the arbiter 13. If a busy signal is off and a bus is released, a new bus master is generated by turning the busy signal off. By turning the BREQ signal off, a read (RD) or write (WT) signal is transmitted. When the RD or WT terminates within a certain period, a value of a response (XACK) signal from a bus slave is stored in a response result memory part 103. If the XACK signal is completed, the operation terminates, and if the XACK signal is not completed, retrial is executed. |
