摘要 |
<p>The system has two data train generators one of which (1FG2) is controlled by a timing pulse source (CL) so as to produce digital data for branches (bi1-bi3). This data, for each digital word and each group of bits (b1-8, b9-12) determines towards which branches (B1-B4) the word and bit groups are to be directed. The system uses memory elements which include word registers and bit group registers (BR1-BR4) whose data inputs are connected to the other data train generator (IFG1). The data outputs of each register form the depart point of a processing branch. The word and bit group registers, to which only a part of the input data train is routed, have their trigger inputs (A) connected to a blocking element (AND1-AND3). These blocking elements are designed to prevent the passage of clock pulses as a function of the corresponding data routed to the respective processing branches.</p> |