发明名称 |
DETECTING SYSTEM OF FRAME SYNCHRONIZING SIGNAL |
摘要 |
PURPOSE:To shorten the frame pull-in time by making use of a block synchronizing signal to detect a frame synchronizing signal. CONSTITUTION:The ''1'' signal which is inserted every (m+1) bits is detected out of a signal train supplied from a terminal 41 through a block synchronizing circuit 3. Then a block synchronizing signal corresponding to the ''1'' signal is outputted. A frame synchronizing circuit 4 detects a frame synchronizing signal by means of the block synchronizing signal sent from the circuit 3. |
申请公布号 |
JPS60201755(A) |
申请公布日期 |
1985.10.12 |
申请号 |
JP19840057986 |
申请日期 |
1984.03.26 |
申请人 |
NIPPON DENSHIN DENWA KOSHA |
发明人 |
YAMADA JIYUNICHI;KITSUKAI NORIAKI;NAKAGAWA SEIJI |
分类号 |
H04J3/06 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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