| 摘要 |
<p>A computer system having a central processor unit, a main memory for storage of information and a master control unit connected between the processor and memory. The master control unit intercepts and interprets virtual addresses and commands issued by the central processor in such a way that one class of virtual addresses and commands are interpreted to be associated with reading of information and writing of information from the main memory and are translated into real addresses issued by the master control unit to the main memory and a second class of virtual addresses cause autonomous signal routing, transfer and reception activity to be performed by the master control unit. The master control unit performs signal reception independently of the central processor and initiates operation of the central processor when the received signal has been accepted by the master control unit, the master control unit being able to access the main memory independently in performing such signalling activities.</p> |
