发明名称 SEMICONDUCTOR MEMORY CELL
摘要 PURPOSE:To contrive speed-up and the increase in degree of operating margin by a method wherein a capacitor made of a Schottky barrier diode is connected in parallel with loads. CONSTITUTION:The titled device is the same as the conventional one except the point of addition of a p type region 21. The load resistor is made of a base layer 14 between electrodes 13 and 20, and the diode is formed between p type regions 14, 19 and n type regions 15, 17. Since the high concentration p-layer 21 and the high concentration n-layer form a p-n junction, the capacitor CL put in parallel with the diode can be made very large. In the case of a Fig. (b), the SBD is formed between a metallic electrode 20 and an n type layer 22; however, in this invention, CL is made large by using a high concentration n- layer as the region 22.
申请公布号 JPS60258954(A) 申请公布日期 1985.12.20
申请号 JP19850082350 申请日期 1985.04.19
申请人 HITACHI SEISAKUSHO KK 发明人 HONMA NORIYUKI;YAMAGUCHI KUNIHIKO;ISOBE TERUO;KITSUKAWA GOROU
分类号 G11C11/411;H01L21/822;H01L21/8229;H01L27/04;H01L27/10;H01L27/102 主分类号 G11C11/411
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