| 摘要 |
PURPOSE:To cope with a high data input/output speed of a channel processor by providing a 2-stage register corresponding to each channel between a register of each channel and a common buffer memory and setting the data width of the 2-stage register at the value equal to the word width of each access of the buffer memory. CONSTITUTION:For data input, the 1-byte data received by a register 3 is transferred by a control part 12 to the sequential byte position of a register 10. The dta on the register 10 is transferred to a register 11 every byte through a control part 13 serving as the 1st common transfer mechanism. When four bytes are transferred to the register 11, the 4-byte data of the register 11 is written on a buffer memory 6 through a control part 14 serving as the 2nd common transfer mechanism. For data output, the 4-byte data is read out of the memory 6 by the part 14 and transferred to the register 11. Then the part 13 transfers the data every byte to the register 10, and the part 12 sets this data every byte to the register 3 from the register 10. |
