| 摘要 |
PURPOSE:To detect a watchdog timer signal in case of a by storing the execution time for sequence operation to a CPU to carry out the delivery of a start instruction for operation, the counting action of reference clocks until the end of the operation and the resetting action when the operation is over. CONSTITUTION:When a chip selection (CS) signal, a write/read (WR) signal and a reference clock are all supplied to an NAND circuit 3. Then a start command is given to the LOAD terminal of a sequence controller 1 through an output terminal 3a. Thus an operation is carried out by the sequence program of LOAD, CD and A-D respectively. The controller 1 is reset by a reset signal as soon as the operation is over. At the same time, a counter for reference clocks 2 is cleared. The operation is discontinued if the CPU has a fault during the execution of a sequence operation. Then a watchdog timer signal WDT is delivered through a CARRY terminal. |
