发明名称 FAIL-SAFE PROCESSOR SYSTEM
摘要 PURPOSE:To make a fail-safe processor system practicable by converting always processor bus signals into analogs and also by comparing converted analog values with reference values through a fail-safe analog comparator. CONSTITUTION:At normal time, double series microcomputers 10 and 20 operate almost synchronously and the outputs coming from digital-analog converters 30A and 30B are nearly the same level having little deviation. Thus a failure detection relay FSAC detects that the comparator 31 normally oscillates. If data discrepancies occur, the outputs values coming from digital-analog converters 30A and 30B are so different that the comparator 31 stops oscillating. Accordingly, the failure detection relay FDA, being lacking in an exciting function, can detect any fail-safe failure of the double series microcomputers.
申请公布号 JPS61195433(A) 申请公布日期 1986.08.29
申请号 JP19850037037 申请日期 1985.02.26
申请人 HITACHI LTD 发明人 SAITO KUNIO;TASHIRO FUSASHI;SATO HIROSHI;MORITA YUZO
分类号 G06F11/18;G06F11/16 主分类号 G06F11/18
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