发明名称 COMPLEMENTARY INSULATED GATE FIELD EFFECT TRANSISTOR INTEGRATED CIRCUIT AND MANUFACTURE THEREOF
摘要 PURPOSE:To reduce a variation in a threshold value voltage due to a variation in a gate length by forming a length of an electrode material layer in a channel direction longer than a portion relating to an n-channel transistor at a portion relating to a p-channel transistor. CONSTITUTION:The length of a gate electrode of a p-channel MOS transistor is formed longer than that of an n-channel MOS transistor so that the effective lengths Lne, Lpe of the channels are equalized. Accordingly, if the length L of the electrode is varied when forming the electrode by etching, when a variation in the length L of the same value occurs in the p-channel and n-channel transistors, since the length L is longer in the p-channel transistor, the variation rate of the length L is small. On the other hand, since the length L is shorter in the n-channel transistor, a variation rate of the length L is large. Thus, a variation in a threshold value voltage Vt can be reduced to improve a yield of a product.
申请公布号 JPS62125661(A) 申请公布日期 1987.06.06
申请号 JP19850263906 申请日期 1985.11.26
申请人 FUJI PHOTO FILM CO LTD 发明人 SHIZUKUISHI MAKOTO;KONDO RYUJI
分类号 H01L27/092;H01L21/8238;H01L29/78 主分类号 H01L27/092
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