| 摘要 |
PURPOSE:To allow a microprocessor to execute the substantial data processing and to cope with a wide range transmission speed by frequency-dividing an external clock pulse, using the result as an internal clock pulse and outputting a required parallel data. CONSTITUTION:A muCPU1(14-16) processes a required data and outputs a transmission command signal and a parallel data synchronously. A frequency divider 2 frequency-divides an external clock pulse by a prescribed frequency division ratio, supplies the result to a binary counter CT4, which forms a required internal clock pulse and supplies it to shift registers SR101-103 and data bit CTs 51, 52. Then a parallel data is loaded to each SR by a read command signal and the serial data is outputted by the shift operation. A transmission operation control section 9 uses the transmission command signal to activate the CT4, the operation of the CT4 is stopped by a transmission end signal from the CT52, the transmission end signal is sent to the CPU1 to control the transmission operation. |
