发明名称 MEMORY ADDRESS CONTROL SYSTEM FOR CHANNEL DEVICE
摘要 PURPOSE:To continue data transfer between a main memory and a channel without interruption by latching the output from a page boundary detecting part and setting a next page memory address effective display latch while data is transferred. CONSTITUTION:At every time data is transferred once between the main memory and the channel, the main memory address is updated by a counter 23 and is set again to a current memory address register 22 through a selector 21. The output of the counter 23 is given to a page boundary detecting part 24; and if the current memory address exceeds the page boundary while data is transferred, a detection signal is outputted from the detecting part 24. If a next page memory address effective display latch 26 is set in this case, the selector 21 selects the output of a next page memory address register 20 by the outputs of an AND gate 27 and an OR gate 28. As the result, the main memory address of the next page is stored in the register 22.
申请公布号 JPS62251943(A) 申请公布日期 1987.11.02
申请号 JP19860096561 申请日期 1986.04.25
申请人 HITACHI LTD 发明人 JINNO KEIJI;OSAKA HIROSHI
分类号 G06F12/10;G06F12/08;G06F13/12 主分类号 G06F12/10
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