| 摘要 |
PURPOSE:To increase the response speed of an A/D converter, and to improve resolution by providing a frequency dividing circuit which divides the frequency of driving pulses on receiving a start signal, and then counting its output by a counting circuit. CONSTITUTION:The output QA of a 1/2 frequency divider 13 rises synchronizing with the 5th rise of a pulse P1. Therefore, the 1st-4th pulses before a system is balanced are disregarded. When the output QA of the 1/2 frequency divider 13 rises to a ''1'', a gate 4' generates the output of AND between a count pulse P2 and the output V2 of a comparator 3. The output QA of the 1/2 frequency divider 13 is inverted in synchronizing with the 10th fall of the pulse P1 and the system stops operating. A counting circuit 16 counts the output V3 of the gate 4'. An arithmetic circuit 17 receives the output of the counting circuit 16 to perform arithmetic, and then converts the result into a digital value which corresponds to a signal Ex to be measured. |
