发明名称 FUNCTION DESCRIPTION DEVELOPMENT SYSTEM
摘要 PURPOSE:To delete the number of processes required at the time of forming basic logical circuit connection information and to prevent the formation of a logical bug by automatically forming the connection information between the basic logical circuits from the description of a function. CONSTITUTION:A function description input part supplies the function description 10 to a function description analyzing part 12 to analyze the connection relation of respective signals and an input and output signal to respective operators. A connection information between operators forming part 13 forms the connection information between the operators based on an analyzing result (a) and outputs an operator development result (d) through an operator analyzing part 14 and an operator development part 15. A connection information between basic operators forming part 16outputs the connection information between the basic operators from the result (d) and the connection information (e) and substitutes the basic logical circuit suitable for the operator through a basic logical circuit substitution part 18. A connection information between basic logical circuits forming part 19 forms the basic logical circuit connection information from a substitution result (g) and connection information (h) between the operators and outputs.
申请公布号 JPS62293473(A) 申请公布日期 1987.12.21
申请号 JP19860137389 申请日期 1986.06.12
申请人 NEC CORP 发明人 KURASHITA MASAHIRO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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