| 摘要 |
PURPOSE:To decrease the timewise delay in a signal of a bus line even if the leading edge and trailing edge times of a signal waveform on the bus have a delay by providing an inverter group on the way of the bus line. CONSTITUTION:Input signals 201, 202 and an output signal 205 act like negative logic and input signals 203, 204 and an output signal 206 act as positive logic. With a clock signal 101 at a low level, buses 3, 4 are discharged and precharged respectively, and with the signal 101 at a high level, the transmission/reception of the signal is executed. That is, with the signal 101 at a high level and with the input signals 201, 202 at a low level, the output signals 205, 206 go respectively to low and high levels and with the input signals 203, 204 at a high level, the output signals 205, 206 go respectively to low and high level. Since a MOS inverter has the effect for shaping the signal waveform in general, the time delay of the signal on the bus line is decreased.
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