发明名称 緩衝記憶装置及び信号処理回路
摘要 It is an object to provide a signal processing circuit for which a complex manufacturing process is not necessary and whose power consumption can be suppressed. In particular, it is an object to provide a signal processing circuit whose power consumption can be suppressed by stopping the power supply for a short time. The signal processing circuit includes a control circuit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit; the buffer memory device comprises a plurality of memory cells; and the memory cells each include a transistor including an oxide semiconductor in a channel formation region and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor.
申请公布号 JP6030298(B2) 申请公布日期 2016.11.24
申请号 JP20110274252 申请日期 2011.12.15
申请人 株式会社半導体エネルギー研究所 发明人 黒川 義元
分类号 G11C11/401;G06F12/08;G11C11/405;H01L21/8242;H01L27/108;H01L29/786 主分类号 G11C11/401
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