| 摘要 |
A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams. |
| 主权项 |
1. An apparatus comprising:
an instruction converter to convert each occurrence of an instruction of a first instruction set that has a first instruction format into one or more corresponding instructions of a second different instruction set, wherein the first instruction format includes a first plurality of templates that each include a plurality of fields including a base operation field, a data element width (W) field, a vector length field, a write mask control field, and a write mask field, wherein the first instruction format supports through different values in the base operation field specification of a plurality of different vector operations, wherein each of the plurality of vector operations requires an operation to be independently performed on each of a plurality of different data element positions of at least one source vector operand to generate at least one destination vector operand, wherein the first instruction format supports through different values in the data element width field specification of a 32 bit and a 64 bit data element width, wherein the first plurality of templates support through different values in the vector length field specification of a plurality of different vector lengths, wherein the first instruction format supports through different values in the write mask field specification of different write masks, wherein the first instruction format supports through different values in the write mask control field selection between merging write mask and zeroing write mask, wherein only one of the different values is placed in each of the base operation field, the data element width field, the write mask control field, and the write mask field on each said occurrence of the instruction in the first instruction format in instruction streams, the instruction converter to convert the occurrences of the instructions that have the first instruction format that includes the first plurality of templates as follows:
distinguish, for each of the occurrences, which one of the different vector operations to perform based on the base operation field's content;distinguish, for each of the occurrences, which one of the data element widths to use based on the data element width field's content;distinguish, for each of the occurrences, which one of the vector lengths to use based on the vector length field's content;distinguish, for each of the occurrences which one of merging write mask and zeroing write mask to perform based on the write mask control field's content; anddistinguish, for each of the occurrences, which one of the different write masks to use based on the write mask field's content, wherein the data element width and the vector length for the occurrence distinguishes which data element positions correspond with which bits of the occurrence's write mask, wherein the write mask for the occurrence specifies on a per data element position basis whether results of the occurrence's vector operation are or are not to be reflected in the destination vector operand's corresponding data element positions, wherein those of the destination vector operand's corresponding data element positions that correspond to bits of the occurrence's write mask that have a non-zero value reflect the results of the occurrence's vector operation, and wherein those of the destination vector operand's corresponding data element positions that correspond to bits of the occurrence's write mask that have a zero value are set to zero when zeroing write mask is selected; and a processor coupled with the instruction converter, the processor to decode and execute the one or more instructions converted from each occurrence of the instruction of the first instruction set that has the first instruction format. |
